Single Event Effects

A single event effect (SEE) results from, as the term suggests, a single, energetic particle. The possibility of single-event upsets was first postulated by Wallmark and Marcus in 1962.[1] The first actual satellite anomalies were reported by Binder et al. in 1975.[2] Some of the early pioneering work was by May and Woods, who investigated alpha-particle-induced soft errors.[3] In their work the source of alpha particles was not from space but rather from the natural decay of trace (ppm) concentrations of uranium and thorium present in integrated circuit packaging materials.

Single event phenomena can be classified into three effects (in order of permanency):

  1. Single event upset (soft error)
  2. Single event latchup (soft or hard error)
  3. Single event burnout (hard failure)

Single Event Upset

Single event upset (SEU) is defined by NASA as "radiation-induced errors in microelectronic circuits caused when charged particles (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs." [Ref: NASA Thesaurus] SEUs are transient soft errors, and are non-destructive. A reset or rewriting of the device results in normal device behavior thereafter. An SEU may occur in analog, digital, or optical components, or may have effects in surrounding interface circuitry. SEUs typically appear as transient pluses in logic or support circuitry, or as bit flips in memory cells or registers. Also possible is a multiple-bit SEU in which a single ion hits two or more bits causing simultaneous errors. Multiple-bit SEU is a problem for single-bit error detection and correction (EDAC) where it is impossible to assign bits within a word to different chips (e.g., a problem for DRAMs and certain SRAMs). A severe SEU is the single-event functional interrupt (SEFI) in which an SEU in the device's control circuitry places the device into a test mode, halt, or undefined state. The SEFI halts normal operations, and requires a power reset to recover.

[Source: Space Radiation Associates]

Single Event Latchup

Single event latchup (SEL) is a condition that causes loss of device functionality due to a single-event induced current state. Kolasinski et al. first observed SEL in 1979 during ground testing.[4] SELs are hard errors, and are potentially destructive (i.e., may cause permanent damage). The SEL results in a high operating current, above device specifications. The latched condition can destroy the device, drag down the bus voltage, or damage the power supply. Originally, the concern was latchup caused by heavy ions, however, latchup can be caused by protons in very sensitive devices.[5,6] An SEL is cleared by a power off-on reset or power strobing of the device. If power is not removed quickly, catastrophic failure may occur due to excessive heating, or metallization or bond wire failure. SEL is strongly temperature dependent: the threshold for latchup decreases at high temperature, and the cross section increases as well.[7,8]

Single Event Burnout

Single event burnout (SEB) is a condition that can cause device destruction due to a high current state in a power transistor. SEB causes the device to fail permanently. SEBs include burnout of power MOSFETs, gate rupture, frozen bits, and noise in CCDs (charge-coupled devices). SEB of power MOSFETs was first reported by Waskiewicz et al. in 1986.[9] Only SEB of n-channel power MOSFETs has been reported.[10] An SEB can be triggered in a power MOSFET biased in the OFF state (i.e., blocking a high drain-source voltage) when a heavy ion passing through deposits enough charge to turn the device on. SEB susceptibility has been shown to decrease with increasing temperature.[11]

A power MOSFET may undergo single-event gate rupture (SEGR), which is the formation of a conducting path (i.e., localized dielectric breakdown) in the gate oxide resulting in a destructive burnout. Fischer was the first to report on SEGR of power MOSFETs in 1987.[12] SEB can also occur in bipolar junction transistors (BJTs) as was first reported by Titus et al. in 1991.[13] Swift et al. have described a new hard error, that of single-event dielectric rupture (SEDR).[14] SEDR (also referred to as micro-damage) occurs in CMOS and is similar to SEGR observed in power MOSFETs.

Environmental and Design Factors

To estimate the upset rate, one must consider the mechanism by which radiation particles cause the anomaly. The SEUs are caused by two different space radiation sources:

  1. high energy protons, and
  2. cosmic rays, specifically, the heavy ion component of either solar or galactic origins.

The latter heavy ions cause direct ionization within a device. Protons can make a large contribution to the overall upset rate (particularly for LEO). When the feature size is <0.3 µm, then protons will create SEU by direct ionization. Protons typically do not cause an upset through direct ionization, but rather through complex nuclear reactions (spallation) in the vicinity of the sensitive node (see figure below). Spallation is a nuclear reaction in which two or more fragments or particles are ejected from the target nucleus; it is the heavy recoil nuclei ions, such as 25Mg, which can then cause SEU. Example spallation reactions from neutrons and protons include Si(n,a)Mg, Si(n,p)Al [15], Si(p,2p)Al, and Si(p,pa)Mg.[16,17,18]

Schematic showing how galactic cosmic rays deposit energy in an electronic device.
(Source Spacecraft Anomalies due to Radiation Environment in Space by Lauriente and Vampola [19])

Solar flare particle events pose the most extreme SEU producing environment, especially for spacecraft in interplanetary space.[20] Experiments aboard the Combined Release and Radiation Effects Satellite (CRRES) showed a dramatic increase during a solar flare.[21] However, 90% of all SEUs on CRRES were produced by protons contrary to the pre-launch prediction that most upsets would be caused by cosmic rays.[22] Gussenhoven et al. state that based on CRRES data that most single-event upsets come from high energy protons via nuclear interactions and not through direct deposition from either protons or cosmic rays.[23] For LEO satellites, trapped protons, especially in the South Atlantic Anomaly (SAA), are the greatest SEE threat. The SAA, located at 30° S. latitude, 34.5° E. longitude, is shown in the geomagnetic field of Figure 2. Solar cycle activity affects the presence of trapped electrons and protons as shown below:

Solar Min Solar Max
Electron Intensities lower higher
Proton Intensities higher lower

Geomagnetic field at sea level. Note the South Atlantic Anomaly (SAA) which is centered off the southeastern coast of South America
(from the Space Environments & Effects Program at NASA's Marshall Space Flight Center).

Given the division of SEEs into soft and hard errors, it is obvious that permanent hard errors are to be completely avoided. Avoidance may be realized through parts selection and shielding. Unfortunately, shielding is of little value for preventing SEUs. For mitigating soft SEEs, other methods, such as error detection and correction (EDAC), and redundancy, may be employed.

Shielding typically has little effect. Shielding high-energy protons while observing weight restrictions is a difficult task. Adams found that under some conditions that shielding can worsen the problem, since as ions slow down in the shielding their LET increases.[24] Shielding produces significant reductions in soft components like solar flare particles, and moderate reductions in the trapped proton flux. Shielding is ineffective against galactic cosmic rays due to their high energies.

Critical Charge

SEU was first observed in bipolar flip-flops in 1979. Original work in this area was treated with skepticism. SEU has emerged as one of the major issues for application of microelectronics in space. SEU effects have become worse as devices have evolved because of lower “critical charge” due to small device dimensions, and large numbers of transistors per chip and overall complexity. Nichols ranks the susceptibility of current technologies to SEUs:[25]

For GaAs circuits, latchup and burnout do not occur.[26] However, SEU susceptibility is slightly higher in GaAs devices than in Si devices.[27]

Device immunity is determined by its linear energy transfer threshold (LETth). The LETth is defined as the minimum LET to cause a single-event effect at a particle fluence of 107 ions/cm2. SEE-immune is defined as a device having an LETth > 100 MeV·cm˛/mg [28] (~iron threshold, Z>26). Low LETth implies proton sensitivity. If a device is not SEU immune, the device is analyzed for SEU rates and effects as follows:

Device LETth Environment to be Assessed
< 10 MeV·cm˛/mg Cosmic ray ions, trapped protons, solar flare protons
10 - 100 MeV·cm˛/mg Cosmic ray ions
> 100 MeV·cm˛/mg No analysis required

The LETth usually reduces as a device accumulates large TID.[29]

The present trends (e.g., device size and power reduction, line resolution increase, increased memory and speed) will only heighten the SEU susceptibility. This is easily seen when one considers the device as a simple capacitor (C) upon which the ionized particle deposits sufficient charge (Q) to result in a voltage (i.e., logic state) change. SEU occurs when LET > Qcrit.

Since the LETth is equivalent to the LET required to produce a voltage change (DV) sufficient for an SEU, then mathematically:

LETth a DV = Q/C

As the size of these active devices decreases, the capacitance will decrease and so the charge necessary to induce the SEU. The depth of the devices has been generally unchanged; it is the length and width of these devices that have been reduced. If we consider a square device of feature size, L x L, the critical charge for state change is proportional to the feature size squared (Qcrit a L2). Robinson et al. present the measured critical charge for a number of IC technologies (including NMOS, CMOS/bulk CMOS/SOS, i2L, GaAs, ECL, CMOS/SOI, and VHSIC bipolar) as being:[30]

Qcrit = (0.023 pC/µm2) L2

This critical charge is that charge necessary to flip a binary "1" to a "0" or vice-versa, but is less than the total stored charge. Specifically, Qcrit is then the difference between the storage node charge and the minimum charge required for the sensing amplifier to read correctly.[31] In SRAM circuits, Qcrit depends not just on the charge collected but also the temporal shape of the current pulse.

[Source: "Space Radiation Effects on Microelectronics," NASA Jet Propulsion Laboratory]

Elementary Model for Heavy Ions

A very elementary model of SEU behavior can be formed using the concept of LET through some depth of a parallelepiped-shaped device. Start by calculating the energy deposited, Edep, as the particle traverses a chord of length s through the sensitive volume of the device (see diagram below).

Edep = LET p s

The deposited charge depends on the energy required to generate an electron-hole pair, wehp,

Qdep = Edep q / wehp

where q=1.6022x10-19 Coulombs/e and wehp for a few materials are given in the table below:

Properties of intrinsic germanium, silicon, gallium arsenide, silicon dioxide, silicon nitride, and aluminum oxide at 27°C unless otherwise noted.[27]

Material Ge Si GaAs SiO2 Si3N4 Al2O3
Type Semiconductor Semiconductor Semiconductor Insulator Insulator Insulator
Atomic/Molecular Weight 72.6 28.09 144.63 60.08 140.27 101.96
Density (g/cm3) 5.33 2.33 5.32 2.27 3.44 3.97
Electron-hole pair generation energy (eV) 2.8 3.6 4.8 17. 10.8 19.1


Using such a simple approach, a first-order estimate of the minimum LET required for causing an SEU can be computed. Consider a parallelepiped of dimensions a, b, c where c is the device depth. The minimum LET corresponds to the maximum chord length possible, smax, which is the diagonal of the parallelepiped.

s2max = a2 + b2 + c2

The minimum LET necessary to cause an upset can then be calculated from

LETth = Qcrit wehp / (q p smax)

Likewise, there is a minimum distance, smin, that a particle of given LET must travel before being able to deposit sufficient energy to cause an SEU.

smin = Qcrit wehp / (q p LET)

Hence, the particle angle of incidence upon the device is also important. As the incidence angle deviates from normal, the path length traversed by the radiation increases. The angle from incident at which upsets occur for a given particle LET is known as the critical angle, Oc

cos(Oc) = LET / LETC

The particles that produce upset are between an angle of Oc and pi/2. Therefore, there are two potential cases (note LETC < LETth)

  1. If LET > LETC, then all incident angles produce upset.
  2. If LET < LETC, then there is a critical angle, Oc, above which upsets occur.


For a parallelepiped particles incident at an angle O have a path that is 1/cos(O) longer than the path at normal incidence, thus producing more ionization charge. [Note: This "cosine law" fails in some cases, and must be checked for each device technology.] Unlike SEU behavior, SEB and SEGR susceptibility has been shown to decrease with increasing angles of incidence. [7,8,32,33]

The energy deposited per unit path length as an energetic particle travels through a material is the linear energy transfer (LET). Note that the LET is normally defined by dE/dx; however, the LET used in SEU studies is actually the mass stopping power defined by (dE/dx)/p where p is the material density. This results in an LET unit of MeV/(mg/cm2) of material, which is the energy loss per density thickness. Density thickness (td) is the product of the material density and its thickness (t), i.e., td =p·t. Therefore, the density thickness describes the areal density of electrons (electrons/cm2). The LET is dependent on the particle, its energy, and the material traversed.

Practical SEU Calculation

The upset rate may be reported as errors per day per chip, or errors per day per bit (errors/bit-day). Error rates of hardened devices can be of the order of 10-8 errors/bit-day; unhardened devices are generally several orders of magnitude higher.

[Source: "Space Radiation Effects on Microelectronics," NASA Jet Propulsion Laboratory]

There are three basic steps in the calculation of SEU Rates:

  1. Measure the cross section (s) versus LET for example using accelerator testing. The device cross section is defined as the ratio of the number of upsets to the particle fluence. The experimentally determined cross section is a function of particle energy (LET).

    [Source: The Aerospace Corporation SEE Primer]

  2. Determine the sensitive device volume. The sensitive volume is smaller than the actual device physical volume. The sensitive volume is generally different for SEE from heavy ions and protons, as well as SEL. The sensitive geometry and critical charge are the most difficult parameters to determine.
  3. To determine the device error rate, integrate the cross section and sensitive device volume with the LET spectrum.

[Source: The Aerospace Corporation SEE Primer]

In LEO, the inner belt (trapped) protons are the most important source. For LEO satellites, trapped protons, especially in the South Atlantic Anomaly (SAA), are the greatest SEE threat. For GEO, the cosmic and solar particles initiate SEEs. The galactic cosmic ray environment is modeled using CREME; the solar flares can be modeled using JPL or CREME models. Solar flare particle events pose the most extreme SEU producing environment, especially for spacecraft in interplanetary space.[20]

[Source: The NASA ASIC Guide: Assuring ASICS for Space]

The Heinrich Curve above shows the integral energy loss spectrum at GEO. The 100% curve corresponds to solar max condition, and the environment is always worse. The 10% curve combines solar minimum cosmic rays and solar proton activity so that the environment is worse only 10% of the time. The 0.03% curve corresponds to an anomalously large solar flare.

Petersen et al. have developed a simple expression for the upset rate at GEO from galactic rays.[34] The GEO flux is due to galactic cosmic rays since protons at the outer edge of the radiation belts is assumed negligible. SEU error rate expressions are obtained using chord distribution function for the cross section. After integrating the flux and cross section over the range of energies (LET), the "figure of merit" formula for the error rate for the 10% environment results:

R = 5x10-10 ssat / (LETcrit)2

where R is the SEU error rate in errors per bit-day; ssat is the saturation SEU cross section in µm2; and LETcrit is the critical LET in units of pC/µm. For design purposes, the error rate may be estimated using the above expression with ssat = a b with (a,b >> c), and LETcrit=Qcrit/c where c is the silicon device depth, and a and b are its sides in microns (µm). The above expression provides an upper-bound estimate. One can replace the numeral 5 in the “figure of merit” equation with a value of 3.5 for GaAs devices. Multipliers have been developed for the figure of merit (FOM) formula to scale the error rate to other environments, especially solar flares:

Environment Multiplier
Petersen model (SEU figure of merit) 1.0
Galactic model (solar minimum) 0.44
"Ordinary" flare 13
90% worst-case flare 33
Anomalously large flare 5000


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Last updated: January 18, 2006
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